FIG. 1 illustrates the components of a typical eFuse cell. The “eFuse” or fuse 2 in the cell does not act as a typical fuse does by breaking the circuit if it carries too much current. Instead, the eFuse is made with poly-silicon or a similar type of material where the resistance of the fuse can change by allowing a certain amount of current to flow. A high current on the Vfs (“fuse voltage”) pad 16 will increase the resistance of the eFuse 2 from a low of about 300 Ohms to a high of about 1 Mega Ohm.
In addition to the eFuse 2, the eFuse cell of FIG. 1 includes thick oxide transistors 4, 6 and 8, capable of having high voltages across their terminals. The thick oxide is illustrated by the “x” pattern drawn on the gate. Further, a PMOS transistor 10 and inverters 12 and 14 are formed with thin oxide devices, which operate at a lower, typical “core” or system voltage (e.g., 1.0v). The PMOS transistor 10 is illustrated by a gate circle, while NMOS devices 4, 6 and 8 have no gate circle. The Vfs pad 16 is a voltage supply pad shared by all fuses within an array of eFuse cells. The “fs” of “Vfs” stands for fuse to source voltage.
When programming the eFuse cell of FIG. 1, “Read” is held to a logic low or 0, and “Program,” is a logic high or 1. A high programming voltage, for example either 3.3 volts or 2.5 volts, is further applied to “Vfs.” Because “Read” is low and “Pgm” is high, transistors 4 and 8 are then turned off and transistor 6 is on. Current from “Vfs” flows through the node n2, “fuse,” node n1, and transistor 6 to ground. The current created, for example about 10 milliamps, changes the resistance of the fuse 2 from a low of about 300 Ohms to a high of about 1 Mega Ohm. (The main purpose of transistor 8 is to isolate, and therefore protect thin oxide devices from any high voltages on the programming path.)
During reading, “Read” is a logic 1 and “Pgm” is a logic 0. No voltage is supplied on the Vfs pad 16. Thus, transistor 6 is turned off, and transistors 4 and 8 are on. Because the gate of transistor 10 is low, shown as ground, transistor 10 is also on. Thus, transistors 10, 8 and 4 and the fuse 2 in effect form a voltage divider whose output is node n3. Typically, transistors 4 and 8 are designed to be sufficiently strong and have a low impedance so that they do not have an effect on the voltage at node n3, leaving the eFuse device to control the voltage on node n3.
Thus, the voltage on node n3 is a function of transistor 10 and the resistance of eFuse 2 only. For FIG. 1, when the “fuse” is un-programmed, having a low resistance of about 300 ohms, node n3 is at a relatively low voltage, referenced as n3_min. When the eFuse 2 is programmed, having a high resistance, node n3 is at a relatively high voltage, referenced as n3_max. Voltages n3_max and n3_min are between Vdd and ground. Inverter 12 is designed to have a trip point somewhere between n3_min and n3_max so that it, along with inverter 14, can resolve the node n3 voltage to logic 0 or 1 on the output, Data. For example, Data will be a logic 0 if the node n3 voltage is at n3_min for an unprogrammed eFuse because n3_min is less than the inverter 12 trip point.
The 12 inverter trip point varies with process, voltage, and temperature (PVT). The n3_min to n3_max range also varies with PVT, as well as the difference between the un-programmed and programmed resistances of eFuse 2. A disadvantage with having inverter 12 sense the n3 node voltage is that its trip point varies independently of the n3_min to n3_max variation. For example, under some PVT condition it is possible for the n3 min to n3_max range to shift up while the trip point of inverter 12 shifts down. If the trip point shifts below the n3 voltage range, the Data output will always have a logic 1, regardless of the resistance of eFuse 2. It would be desirable to accurately sense the state of the eFuse by having the sensing trip point track the n3 node voltage variations across process, voltage and temperature.